# TPP: Transparent page placement for CXL-enabled tiered-memory

## Meta Info

Presented in [ASPLOS 2023](https://doi.org/10.1145/3582016.3582063).

Authors: Hasan Al Maruf (*UMich*), Hao Wang (*NVIDIA*), Abhishek Dhanotia, Johannes Weiner (*Meta*), Niket Agarwal, Pallab Bhattacharya (*NVIDIA*), Chris Petersen (*Meta*), Mosharaf Chowdhury (*UMich*), Shobhit Kanaujia, Prakash Chauhan (*Meta*).

Code: <https://lwn.net/Articles/876993/>

## Understanding the paper

* **TPP: Transparent Page Placement**
* It characterizes memory usage patterns of applications in Meta.
  * Show the opportunities to *offload colder pages to slower memory tiers*.
* It proposes an OS-level application-transparent pace placement (TPP) for CXL-enabled memory.
  * It identifies and places hot/cold pages to appropriate memory tiers (i.e., local memory or CXL memory).

### Implementation

A major portion of it has been merged to Linux kernel v5.18. The rest of it is under an upstream discussion.

### Evaluation

* Evaluated in the production server fleet with early samples of new x86 CPUs with CXL 1.1.
* Improve application’s performance on default Linux by **18%**.
* Outperforms *NUMA Balancing* and *AutoTiering*, two state-of-the-art tiered-memory management mechanisms, by **5–17%**.


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